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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.1 / feb. 2004 1 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram document title 4bank x 1m x 16bits synchronous dram revision history revision no. history draft date remark 0.1 initial draft february 2004 preliminary
this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.1 / feb. 2004 2 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram description the hynix hy5v66d(l)f(p) series is a 67,108,864bit cmos sy nchronous dram, ideally suited for the memory applica- tions which require wide data i/o and high bandwidt h. hy5v66df6 is organized as 4banks of 1,048,576x16. hy5v66d(l)f(p) is offering fully synchronous operation refere nced to a positive edge of the clock. all inputs and out- puts are synchronized with th e rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. all input and output voltage levels are compatible with lvttl. programmable options include the length of pipeline (read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (burst length of 1,2,4,8 or full page), an d the burst count sequence(se- quential or interleave). a burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or writ e command on any cycle. (this pipelined design is not re- stricted by a '2n' rule) features ? voltage : vdd, vddq 3.3v supply voltage ? all device pins are compatible with lvttl interface ? 54ball fbga ? all inputs and outputs refere nced to positive edge of system clock ? data mask function by udqm, ldqm ? internal four banks operation ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4, 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ? burst read single write operation ordering information part no. clock frequency cas latency organization interface power package hy5v66df-k 133mhz 2 4banks x 1mbits x16 lvttl nornal 54ball fbga, lead hy5v66df-h 133mhz 3 hy5v66df-p 100mhz 2 hy5v66df-s 100mhz 3 hy5v66dfp-k 133mhz 2 54ball fbga, lead free hy5v66dfp-h 133mhz 3 hy5v66dfp-p 100mhz 2 hy5v66dfp-s 100mhz 3 hy5v66dlf-k 133mhz 2 low power 54ball fbga, lead hy5v66dlf-h 133mhz 3 HY5V66DLF-P 100mhz 2 hy5v66dlf-s 100mhz 3 hy5v66dlfp-k 133mhz 2 54ball fbga, lead free hy5v66dlfp-h 133mhz 3 hy5v66dlfp-p 100mhz 2 hy5v66dlfp-s 100mhz 3
rev. 0.1 / feb. 2004 3 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram ball assignments 54 ball fbga 0.8mm ball pitch 9 8 7 3 21 a b c d e f g h j 54 ball fbga 0.8mm ball pitch 9 8 7 3 21 a b c d e f g h j h j b c d a g f e vss dq14 dq12 dq10 dq8 udqm nc a8 vss dq15 dq13 dq11 dq9 nc clk a11 a7 a5 vssq vddq vssq vddq vss cke a9 a6 a4 vddq vssq vddq vssq vdd /cas ba0 a0 a3 dq0 dq2 dq4 dq6 ldqm /ras ba1 a1 a2 vdd dq1 dq3 dq5 dq7 /we /cs a10 vdd 1 2 3 7 8 9 < top view >
rev. 0.1 / feb. 2004 4 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram ball description ball out symbol type description f2 clk input clock : the system clock input. all other inputs are registered to the sdram on the rising edge of clk f3 cke input clock enable : controls internal cloc k signal and when deactivated, the sdram will be one of the states among (deep) power down, suspend or self refresh g9 cs input chip select : enables or disables all inputs except clk, cke, udqm and ldqm g7,g8 ba0, ba1 input bank address : selects bank to be activated during ras activity selects bank to be read/written during cas activity h7, h8, j8, j7, j3, j2, h3, h2, h1, g3, h9, g2 a0 ~ a11 input row address : ra0 ~ ra11, column address : ca0 ~ ca7 auto-precharge flag : a10 f8, f7, f9 ras , cas , we input command inputs : ras , cas and we define the operation refer function truth table for details f1, e8 udqm, ldqm input data mask : controls output buffers in read mode and masks input data in write mode a8, b9, b8, c9, c8, d9, d8, e9, e1, d2, d1, c2, c1, b2, b1, a2 dq0 ~ dq15 i/o data input/output : mu ltiplexed data input/output pin a9, e7, j9, a1, e3, j1 v dd /v ss supply power supply for internal circuits a7, b3, c7, d3, a3, b7, c3, d7 v ddq /v ssq supply power supply for output buffers e2, g1 nc - no connection
rev. 0.1 / feb. 2004 5 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram functional block diagram 1mbit x 4banks x 16 i/o low power synchronous dram internal row counter column pre decoder column add counter self refresh logic & timer sense amp & i/o gate i/o buffer & logic address register burst counter mode register state machine address buffers bank select column active row active cas latency clk cke cs ras cas we u/ldqm a0 a1 ba1 ba0 a11 row pre decoder refresh dq0 dq15 x-decoder x-decoder x-decoder x-decoder y-decoder 1mx16 bank 0 1mx16 bank 1 1mx16 bank 2 1mx16 bank 3 memory cell array data out control pipe line control
rev. 0.1 / feb. 2004 6 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram basic functional description mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0000 op code 00 cas latency bt burst length op code a9 write mode 0burst read and burst write 1 burst read and single write burst type a3 burst type 0 sequential 1 interleave burst length a2 a1 a0 burst length a3 = 0 a3=1 00 0 1 1 00 1 2 2 01 0 44 01 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
rev. 0.1 / feb. 2004 7 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram absolute maximum rating dc operating condition (t a = 0 to 70 o c ) note : 1. all voltages are referenced to v ss = 0v 2. v ih (max) is acceptable 5.6v ac puls e width with <=3ns of duration. 3. v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration ac operating test condition (t a = 0 to 70 o c , v dd =3.3 0.3v, v ss =0v) capacitance (t a = 0 to 70 o c , f=1mhz, v dd =3.3v) parameter symbol rating unit ambient temperature t a 0 ~ 70 o c storage temperature t stg -55 ~ 125 o c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd -1.0 ~ 4.6 v voltage on v ddq relative to v ss v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation pd 1 w soldering temperature . time t solder 260 . 10 o c . sec parameter symbol min typ max unit note power supply voltage v dd, v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.3 v ddq+ 0.3 v 1, 2 input low voltage v il -0.3 - 0.8 v 1, 3 parameter symbol value unit note ac input high/low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage v trip 1.4 v input rise/fall time t r / t f 1ns output timing measurement reference level voltage v outref 1.4 v output load capacitance for access time measurement cl 50 pf 1 parameter pin symbol min max unit input capacitance clk ci1 2.5 4 pf a0 ~ a11, ba0, ba1, cke, cs , ras , cas , we , ldqm, udqm ci2 2.5 5 pf data input / output capaci tance dq0 ~ dq15 ci/o 4 6.5 pf
rev. 0.1 / feb. 2004 8 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram note 1. dc characterristics i (t a = 0 to 70 o c ) note : 1. vin = 0 to 3.3v, all other balls are not tested under vin =0v 2. dout is disabled, vout=0 to 3.6 parameter symbol min max unit note input leakage current i li -1 1 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -2ma output low voltage v ol -0.4v i ol = +2ma vtt=1.4v rt=500 ? 30pf output dc output load circuit ac output load circuit vtt=1.4v rt=50 ? 30pf output z0 = 50 ?
rev. 0.1 / feb. 2004 9 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram dc characteristics ii (t a = 0 to 70 o c ) note : 1. i dd1 and i dd4 depend on output loading and cycle rates. spec ified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii parameter symbol test condition speed unit note -k -h -p -s operating current i dd1 burst length=1, one bank active t rc t rc (min), i ol =0ma 85 80 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 2 ma i dd2ps cke v il (max), t ck = 2ma precharge standby current in non power down mode i dd2n cke v ih (min), cs v ih (min), t ck = 15ns input signals are chan ged one time during 2clks. all other pins v dd -0.2v or 0.2v 15 ma i dd2ns cke v ih (min), t ck = input signals are stable. 12 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 6 ma i dd3ps cke v il (max), t ck = 5 active standby current in non power down mode i dd3n cke v ih (min), cs v ih (min), t ck = 15ns input signals are chan ged one time during 2clks. all other pins v dd -0.2v or 0.2v 30 ma i dd3ns cke v ih (min), t ck = input signals are stable. 20 burst mode operating cur- rent i dd4 t ck t ck (min), i ol =0ma all banks active cl=3 150 120 ma 1 cl=2 120 auto refresh current i dd5 t rc t rc (min), all banks active 160 ma 2 self refresh current i dd6 cke 0.2v normal 1ma low power 400 ua
rev. 0.1 / feb. 2004 10 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram ac characteristics i (ac operating conditions unless otherwise noted) note : 1. assume t r / t f (input rise and fall time) is 1ns. if t r & t f > 1ns, then [(t r +t f )/2-1]ns should be added to the parameter. 2. access time to be measured with input signal s of 1v/ns edge rate, from 0.8v to 0.2v. if t r > 1ns, then (t r /2-0.5)ns should be added to the parameter. parameter symbol k h p s unit note min max min max min max min max system clock cycle time cas latency=3 t ck3 7.5 1000 7.5 1000 10 1000 10 1000 ns cas latency=2 t ck2 7.5 10 10 12 ns clock high pulse width t chw 2.5 - 2.5 - 3.0 - 3.0 - ns 1 clock low pulse width t clw 2.5 - 2.5 - 3.0 - 3.0 - ns 1 access time from clock cas latency=3 t ac3 -5.4-5.4-6.0-6.0 ns 2 cas latency=2 t ac2 -5.4-6.0-6.0-8.0 ns data-out hold time t oh 2.0 - 2.0 - 2.0 - 2.0 - ns data-input setup time t ds 1.5 - 1.5 - 2.0 - 2.0 - ns 1 data-input hold time t dh 0.8 - 0.8 - 1.0 - 1.0 - ns 1 address setup time t as 1.5 - 1.5 - 2.0 - 2.0 - ns 1 address hold time t ah 0.8 - 0.8 - 1.0 - 1.0 - ns 1 cke setup time t cks 1.5 - 1.5 - 2.0 - 2.0 - ns 1 cke hold time t ckh 0.8 - 0.8 - 1.0 - 1.0 - ns 1 command setup time t cs 1.5 - 1.5 - 2.0 - 2.0 - ns 1 command hold time t ch 0.8 - 0.8 - 1.0 - 1.0 - ns 1 clk to data output in low-z time t olz 1.5 - 1.5 - 1.0 - 2.0 - ns clk to data output in high-z time cas latency=3 t ohz3 -5.4-5.4-6.0-6.0ns cas latency=2 t ohz2 -5.4-5.4-6.0-6.0ns
rev. 0.1 / feb. 2004 11 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram ac characteristics ii (ac operating conditions unless otherwise noted) note : 1. a new command can be given t rrc after self refresh exit. parameter symbol k h p s unit note min max min max min max min max ras cycle time operation t rc 65 - 65 - 70 - 70 - ns ras cycle time auto refresh t rrc 65 - 65 - 70 - 70 - ns ras to cas delay t rcd 15 - 20 - 20 - 20 - ns ras active time t ras 45 120k 45 120k 50 120k 50 120k ns ras precharge time t rp 15 - 20 - 20 - 20 - ns ras to ras bank active delay t rrd 15 - 15 - 20 - 20 - ns cas to cas delay t ccd 1-1-1-1-clk write command to data-in delay t wtl 0 -0 -0 -0 -clk data-in to precharge command t dpl 1-1-1-1-clk data-in to active command t dal t dpl + t rp dqm to data-out hi-z t dqz 2-2-2-2-clk dqm to data-in mask t dqm 0-0-0-0-clk mrs to new command t mrd 1-1-1-1-clk precharge to data output high-z cas latency=3 t proz3 3-3-3-3-clk cas latency=2 t proz2 2-2-2-2-clk power down exit time t dpe 1-1-1-1-clk self refresh exit time t sre 1-1-1-1-clk1 refresh time t ref -64-64-64-64ms
rev. 0.1 / feb. 2004 12 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram command truth table command cken-1 cken cs ras cas we dqm addr a10/ap ba note mode register set h x l l l l x op code no operation h x hx xx xx lhhh bank active h x l l h h x ra v read hxlhlhxca l v read with autoprecharge h write hxlhllxca l v write with autoprecharge h precharge all banks hxllhlxx hx precharge selected bank lv burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single-write h x l l l l x a9 ball high (other balls op code) mrs mode self refresh 1 entry h l l l l h x x exit l h hx xx x lhhh precharge power down entry h l hx xx x x lhhh exit l h hx xx x lhhh clock suspend entry h l hx xx x x lvvv exit l h x x
rev. 0.1 / feb. 2004 13 preliminary hy5v66d(l)f(p) series 4banks x 1m x 16bits synchronous dram package information 54 ball 0.8mm pitch 8mm fbga unit [mm] 1.20max 0.340 0.05 0.450 0.05 8.0 6.40bsc 0.80(typ) a1 index mark 8.00 0.80(typ) 6.40 4.00 0.05 bottom view 0.8 3.20 0.05

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